/*!
    \file    change log.txt
    \brief   change log for GD32VF10x firmware

    \version 2026-02-05, V1.70, firmware for GD32VF103
*/

/*
    Copyright (c) 2026, GigaDevice Semiconductor Inc.

    Redistribution and use in source and binary forms, with or without modification, 
are permitted provided that the following conditions are met:

    1. Redistributions of source code must retain the above copyright notice, this 
       list of conditions and the following disclaimer.
    2. Redistributions in binary form must reproduce the above copyright notice, 
       this list of conditions and the following disclaimer in the documentation 
       and/or other materials provided with the distribution.
    3. Neither the name of the copyright holder nor the names of its contributors 
       may be used to endorse or promote products derived from this software without 
       specific prior written permission.

    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
OF SUCH DAMAGE.
*/

******************* V1.6.0 2025-08-07 ******************************************************************************************

______________________Module FMC________________________________________________________________________________________________
/GD32VF103_Firmware_Library/Examples/FMC/Erase_Program/main.c
fix reason: 
Erase all flags before programming
V1.6.0:
None
V1.7.0:
    /* clear all pending flags */
    fmc_flag_clear(FMC_FLAG_END);
    fmc_flag_clear(FMC_FLAG_WPERR);
    fmc_flag_clear(FMC_FLAG_PGERR);
__________________________________________________________________________________________________________________________

______________________Module PMU______________________________________________________________________________________________
/GD32VF103_Firmware_Library/Examples/PMU/Deepsleep_wakeup_RTC/main.c
/GD32VF103_Firmware_Library/Examples/PMU/Deepsleep_wakeup_exti/main.c
/GD32VF103_Firmware_Library/Examples/PMU/Standby_wakeup_RTC/main.c
/GD32VF103_Firmware_Library/Examples/PMU/Standby_wakeup_pin/main.c

fix reason: 
add switch frequence code to prevent vcore fluctuations
V1.6.0:
none
V1.7.0:
1.
/* software delay to prevent the impact of Vcore fluctuations.
   It is strongly recommended to include it to avoid issues caused by self-removal. */
static void _soft_delay_(uint32_t time)
{
    __IO uint32_t i;
    for(i=0; i<time*10; i++){
    }
}
2.
        /* The following is to prevent Vcore fluctuations caused by frequency switching. 
           It is strongly recommended to include it to avoid issues caused by self-removal. */
        rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV2);
        _soft_delay_(0x50);
        rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV4);
        _soft_delay_(0x50);
        rcu_system_clock_source_config(RCU_CKSYSSRC_IRC8M);
        _soft_delay_(200);
        rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV1);

__________________________________________________________________________________________________________________________

______________________Module FWDGT___________________________________________________________________________________
/GD32VF103_Firmware_Library/Examples/FWDGT/FWDGT_key/main.c
fix reason: 
First enable the FWDGT, then write PSC and RLD, and wait for RUD and PUD to clear.
V1.6.0:
    /* after 1.6 seconds to generate a reset */
    fwdgt_enable();
V1.7.0:
None

/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c
fix reason: 
First enable the FWDGT, then write PSC and RLD, and wait for RUD and PUD to clear.
V1.6.0:
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value) {
    uint32_t timeout = FWDGT_PSC_TIMEOUT;
    uint32_t flag_status = 0U;

    /* enable write access to FWDGT_PSC */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* wait until the PUD flag to be reset */
    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
    } while ((--timeout > (uint32_t) 0) && (0U != flag_status));

    if (0U != flag_status) {
        return ERROR;
    }

    /* configure FWDGT */
    FWDGT_PSC = (uint32_t) prescaler_value;

    return SUCCESS;
}

/*!
 \brief      configure the FWDGT counter reload value
 \param[in]  reload_value: specify reload value(0x0000 - 0x0FFF)
 \param[out] none
 \retval     ErrStatus: ERROR or SUCCESS
 */
ErrStatus fwdgt_reload_value_config(uint16_t reload_value) {
    uint32_t timeout = FWDGT_RLD_TIMEOUT;
    uint32_t flag_status = 0U;

    /* enable write access to FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* wait until the RUD flag to be reset */
    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
    } while ((--timeout > 0U) && (0U != flag_status));

    if (0U != flag_status) {
        return ERROR;
    }

    FWDGT_RLD = RLD_RLD(reload_value);

    return SUCCESS;
}

/*!
 \brief      reload the counter of FWDGT
 \param[in]  none
 \param[out] none
 \retval     none
 */
void fwdgt_counter_reload(void) {
    FWDGT_CTL = FWDGT_KEY_RELOAD;
}

/*!
 \brief      configure counter reload value, and prescaler divider value
 \param[in]  reload_value: specify reload value(0x0000 - 0x0FFF)
 \param[in]  prescaler_div: FWDGT prescaler value
 only one parameter can be selected which is shown as below:
 \arg        FWDGT_PSC_DIV4: FWDGT prescaler set to 4
 \arg        FWDGT_PSC_DIV8: FWDGT prescaler set to 8
 \arg        FWDGT_PSC_DIV16: FWDGT prescaler set to 16
 \arg        FWDGT_PSC_DIV32: FWDGT prescaler set to 32
 \arg        FWDGT_PSC_DIV64: FWDGT prescaler set to 64
 \arg        FWDGT_PSC_DIV128: FWDGT prescaler set to 128
 \arg        FWDGT_PSC_DIV256: FWDGT prescaler set to 256
 \param[out] none
 \retval     ErrStatus: ERROR or SUCCESS
 */
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) {
    uint32_t timeout = FWDGT_PSC_TIMEOUT;
    uint32_t flag_status = RESET;

    /* enable write access to FWDGT_PSC,and FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
    /* wait until the PUD flag to be reset */
    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
	} while ((--timeout > 0U) && ((uint32_t) RESET != flag_status));

	if ((uint32_t) RESET != flag_status) {
		return ERROR;
	}
	/* configure FWDGT */
	FWDGT_PSC = (uint32_t) prescaler_div;

	timeout = FWDGT_RLD_TIMEOUT;
	/* wait until the RUD flag to be reset */
	do {
		flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
	} while ((--timeout > 0U) && ((uint32_t) RESET != flag_status));

	if ((uint32_t) RESET != flag_status) {
		return ERROR;
	}
	FWDGT_RLD = RLD_RLD(reload_value);
	/* reload the counter */
	FWDGT_CTL = FWDGT_KEY_RELOAD;

	return SUCCESS;
}
V1.7.0:
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value) {
    uint32_t timeout = FWDGT_PSC_TIMEOUT;
    uint32_t flag_status = 0U;
    ErrStatus status = SUCCESS;

    /* enable write access to FWDGT_PSC */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
 
    /* configure FWDGT */
    FWDGT_PSC = (uint32_t) prescaler_value;

    /* wait until the PUD flag to be reset */
    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
    } while ((--timeout > (uint32_t) 0) && (0U != flag_status));

    if (0U != flag_status) {
        status = ERROR;
    }
    return status;
}

/*!
 \brief      configure the FWDGT counter reload value
 \param[in]  reload_value: specify reload value(0x0000 - 0x0FFF)
 \param[out] none
 \retval     ErrStatus: ERROR or SUCCESS
 */
ErrStatus fwdgt_reload_value_config(uint16_t reload_value) {
    uint32_t timeout = FWDGT_RLD_TIMEOUT;
    uint32_t flag_status;
    ErrStatus status = SUCCESS;

    /* enable write access to FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* configure FWDGT_RLD */
    FWDGT_RLD = RLD_RLD(reload_value);

    /* wait until the RUD flag to be reset */
    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
    } while((--timeout > 0U) && (0U != flag_status));

    if(0U != flag_status) {
        status = ERROR;
    }

    return status;
}

/*!
 \brief      reload the counter of FWDGT
 \param[in]  none
 \param[out] none
 \retval     none
 */
void fwdgt_counter_reload(void) {
    FWDGT_CTL = FWDGT_KEY_RELOAD;
}

/*!
 \brief      configure counter reload value, and prescaler divider value
 \param[in]  reload_value: specify reload value(0x0000 - 0x0FFF)
 \param[in]  prescaler_value: FWDGT prescaler value
 only one parameter can be selected which is shown as below:
 \arg        FWDGT_PSC_DIV4: FWDGT prescaler set to 4
 \arg        FWDGT_PSC_DIV8: FWDGT prescaler set to 8
 \arg        FWDGT_PSC_DIV16: FWDGT prescaler set to 16
 \arg        FWDGT_PSC_DIV32: FWDGT prescaler set to 32
 \arg        FWDGT_PSC_DIV64: FWDGT prescaler set to 64
 \arg        FWDGT_PSC_DIV128: FWDGT prescaler set to 128
 \arg        FWDGT_PSC_DIV256: FWDGT prescaler set to 256
 \param[out] none
 \retval     ErrStatus: ERROR or SUCCESS
 */
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_value) {
    uint32_t timeout = FWDGT_PSC_TIMEOUT;
    uint32_t flag_status;
    ErrStatus status = SUCCESS;

    /* start the free watchdog timer counter */
    FWDGT_CTL = FWDGT_KEY_ENABLE;

    /* enable write access to FWDGT_PSC,and FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* configure FWDGT_PSC */
    FWDGT_PSC = (uint32_t)prescaler_value;

    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
    } while((--timeout > 0U) && (0U != flag_status));

    if(0U != flag_status) {
        status = ERROR;
    }

    if(SUCCESS == status) {
        /* configure FWDGT_RLD */
        FWDGT_RLD = RLD_RLD(reload_value);

        /* wait until the RUD flag to be reset */
        timeout = FWDGT_RLD_TIMEOUT;
        do {
            flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
        } while((--timeout > 0U) && (0U != flag_status));

        if(0U != flag_status) {
            status = ERROR;
        }
    }

    if(SUCCESS == status) {
        /* reload the counter */
        FWDGT_CTL = FWDGT_KEY_RELOAD;
    }

    return status;
}

/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h
fix reason: 
First enable the FWDGT, then write PSC and RLD, and wait for RUD and PUD to clear.
V1.6.0:
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
V1.7.0:
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_value);
__________________________________________________________________________________________________________________________

______________________CAN________________________________________________________________________________________________
/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h
fix reason: 
modify the CAN register MACRO

V1.6.0:
#define CAN_F23DATA0(canx)                 REG32((canx) + 0x3F8U) 
V1.7.0:
#define CAN_F23DATA0(canx)                 REG32((canx) + 0x2F8U)  
__________________________________________________________________________________________________________________________

______________________BKP________________________________________________________________________________________________
/GD32VF103_Firmware_Library/Examples/BKP/Backup_Data/main.c
/GD32VF103_Firmware_Library/Examples/BKP/Tamper/main.c
fix reason: 
If the RCU_BDCTL_BKPRST bit is set, reading BKP_DATAx will cause the MCU to crash or run away. 
Before accessing the backup domain content, it is necessary to check whether the RCU_BDCTL_BKPRST bit has been cleared. If it is set, clear it first.

V1.6.0:
None
V1.7.0:
    /* confirm RCU_BDCTL_BKPRST bit is reset */
    if(RESET != (RCU_BDCTL & RCU_BDCTL_BKPRST)){
        rcu_bkp_reset_disable();
    }
__________________________________________________________________________________________________________________________

******************* V1.6.0 2025-08-07 ******************************************************************************************
______________________Module CAN______________________________________________________________________________________________
Fix file:
../GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c
fix reason:
Fix the CAN DLC bug
V1.5.0:
none
V1.6.0:

    /* Classic CAN frame data lenth does not exceed 8 */
    if (transmit_message->tx_dlen > 8U) {
        transmit_message->tx_dlen = 8U;
    }


______________________Module USART______________________________________________________________________________________________
Fix file:
../GD32VF103_Firmware_Library/Examples/USART/Half_duplex_transmitter&receiver/main.c
fix reason:
Modify the pin configuration for half-duplex mode
V1.5.0:
/* configure USART0 Tx as alternate function push-pull */
gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
/* configure USART1 Tx as alternate function push-pull */
gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2);
V1.6.0:
/* configure USART0 Tx as alternate function open-drain */
gpio_init(GPIOA, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
/* configure USART1 Tx as alternate function open-drain */
gpio_init(GPIOA, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_2);

Fix file:
../GD32VF103_Firmware_Library/Examples/USART/Half_duplex_transmitter&receiver/readme.txt
fix reason:
Modify the pin configuration for half-duplex mode
V1.5.0:
connect  USART0_Tx(PA9) to USART1_Tx(PA2)
JP5 and JP6 must be fitted.
V1.6.0:
connect  USART0_Tx(PA9) to USART1_Tx(PA2), and jumper to PB7 with a pull-up resistor.
JP5 and JP6 must be fitted.
__________________________________________________________________________________________________________________________

________________________Module USB _______________________________________________________________________________________
Fix file:
../GD32VF103_Firmware_Library/Firmware/GD32VF103_usbfs_library/driver/Source/drv_usb_dev.c
fix reason: 
Revise the description.
V1.5.0:
    uint32_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES;
V1.6.0:
    uint32_t enum_speed = ((udev->regs.dr->DSTAT & DSTAT_ES) >> 1);

Fix file:
../GD32VF103_Firmware_Library/Examples/USBFS/USB_Device/dev_firmware_update/Source/system_gd32vf103.c
../GD32VF103_Firmware_Library/Examples/USBFS/USB_Device/in_application_program_hid/Source/system_gd32vf103.c
../GD32VF103_Firmware_Library/Examples/USBFS/USB_Device/msc_cdrom/Source/system_gd32vf103.c
../GD32VF103_Firmware_Library/Examples/USBFS/USB_Device/msc_udisk/Source/system_gd32vf103.c
../GD32VF103_Firmware_Library/Examples/USBFS/USB_Device/standard_hid_mouse/Source/system_gd32vf103.c
../GD32VF103_Firmware_Library/Examples/USBFS/USB_Device/usb_printer/Source/system_gd32vf103.c
../GD32VF103_Firmware_Library/Examples/USBFS/USB_Host/usb_host_keyboard_mouse/Source/system_gd32vf103.c
../GD32VF103_Firmware_Library/Examples/USBFS/USB_Host/usb_host_msc_udisk/Source/system_gd32vf103.c
fix reason:
add clock switch cod
V1.5.0:
none
V1.6.0:
/* The following is to prevent Vcore fluctuations caused by frequency switching. 
   It is strongly recommended to include it to avoid issues caused by self-removal. */
#define RCU_MODIFY_DE_2(__delay)  do{                                     \
                                      volatile uint32_t i,reg;            \
                                      if(0 != __delay){                   \
                                          /* Insert a software delay */   \
                                          for(i=0; i<__delay; i++){       \
                                          }                               \
                                          reg = RCU_CFG0;                 \
                                          reg &= ~(RCU_CFG0_AHBPSC);     \
                                          reg |= RCU_AHB_CKSYS_DIV2;     \
                                          /* AHB = SYSCLK/2 */           \
                                          RCU_CFG0 = reg;                \
                                          /* Insert a software delay */  \
                                          for(i=0; i<__delay; i++){      \
                                          }                              \
                                          reg = RCU_CFG0;                \
                                          reg &= ~(RCU_CFG0_AHBPSC);     \
                                          reg |= RCU_AHB_CKSYS_DIV4;     \
                                          /* AHB = SYSCLK/4 */           \
                                          RCU_CFG0 = reg;                \
                                          /* Insert a software delay */  \
                                          for(i=0; i<__delay; i++){      \
                                          }                              \
                                      }                                  \
                                  }while(0)
____________________________________________________________________________________________________________________________________

